The present invention disclosed herein relates to a connection between a selection bit line and a non-selection bit line of a non-volatile semiconductor memory array and a sense (or, detect) line and a reference sense line of a sense circuit. In more detail, the present invention relates to a semiconductor memory device includes a column decoder circuit. The column decoder circuit maintains a capacity balance to the maximum with respect to a sense line and a reference sense line and is mutually connected, without an increase of a column pre-decoder circuit.
As disclosed in the patent document 1 (Japanese Patent Publication No. 2002-8386), in a non-volatile semiconductor memory, one of a plurality of bit lines constituting a memory array is selectively connected to one of main bit lines, and one of a plurality of main bit lines is selectively connected to one of data lines. Additionally, a sense line of a differential amplifier constituting a sense circuit is connected to a data line and a reference sense line is connected to a reference data line in order to confirm data read from a memory cell.
In the differential amplifier constituting the sense circuit, in an aspect of tolerance with respect to a reading speed or noise, it is important to obtain capacity balance by accurately adjusting a capacity of the reference sense line to a capacity of a sense line. However, if a dummy capacity is used to adjust a capacity of the reference sense line to a capacity of the sense line, it is difficult to accurately adjust the capacity and also positions where a capacity is disposed are different. Therefore, it is vulnerable to noise and also a demerit occurs in terms of an area.
Therefore, according to the patent document 1, first and second column trees include a memory array having first and second memory cells and a line group to which data of the first and second memory cells are delivered. Additionally, once the first memory cell is selected, the first column tree is connected to a sense signal input terminal of the differential amplifier and the second column tree is connected to the reference signal input terminal in order to obtain a capacity balance. From now on, its structure will be described.
FIG. 2 is a memory block diagram illustrating a structure of a memory array acquiring a capacity balance between a sense line and a reference sense line of a differential amplifier. In FIG. 2, a first column tree is a line group to which data of the first memory cell are delivered and includes a first intermediate data line IDL01, a main bit line MBL0-01, and bit lines Bi:BL0, Bi:BL1, Bj:BL0, and Bj:BL1. A second column tree is a line group to which data of another memory cell are delivered and includes a second intermediate data line IDL23, a main bit line MBL0-23, and bit lines Bi:BL2, Bi:BL3, Bj:BL2, and Bj:BL3. A memory cell (not shown) is connected to the bit line BL to constitute the memory array.
Expansion of the memory array is completed by first column gates 0103-Bi:1 and 0103-Bj:1 (in a dashed line) having the above structure, in order to constitute blocks Bi and Bj, respectively. Therefore, since a second column gate 0105 is selected by a second column selection D1 of a second column selection decoder 0104, main bit lines MBL1-01 and MBL1-23 are connected to the first intermediate data lines IDL01 and IDL23, respectively.
Next, selection of the bit line BL will be described. a first column selection decoder 0102 decodes an inner address signal for column selection and selects one of a plurality of column selection signals Bi:H0 to Bi:H3 and Bj:H0 to Bj:H3 to activate it. Due to this, a gate of one of the first column gates 0103-Bi:0 and 0103-Bj:0 is turned on and one of the bit lines Bi:BL0 to Bi:BL3 and BJ:BL0 to Bj:BL3 is connected to one of the main bit lines MBL0-01 and MBL0-23. At this point, since the second column selection decoder 0104 is activated by a second column selection signal D0, the main bit line MBL0-01 is connected to the first intermediate data line IDL01 and the main bit line MBL0-23 is connected to the second intermediate data line IDL23.
A column shift selection decoder 0106 decodes an inner address signal for column selection and selects one of first column shift signals SW01 and SW23. When a memory cell in the first column tree is selected, the shift signal SW01 is set to be high and the shift signal SW23 is set to be low. Because of this, the first intermediate data line IDL01 is connected to the data line DL. Simultaneously, the second intermediate data line IDL23 is connected to the reference data line RDL. When a memory cell in the second column tree is selected, the shift signal SW01 is set to be low and the shift signal SW23 is set to be high. The second intermediate data line IDL23 is connected to the data line DL. Simultaneously, the first intermediate data line IDL01 is connected to the reference data line RDL.
Moreover, the data line DL is connected to the sense signal input terminal of the differential amplifier in the sense circuit, and the reference data line RDL is connected to a reference signal input terminal (not shown). Thus, one (including a memory cell selected to be read) of the first and second column trees is connected to the data line DL, and another tree is connected to the reference data line RDL. Because of this, structures of the first and second column trees are the same and their capacities are the same also. Accordingly, capacity added to the data line DL and the reference data line RDL may be the same and thus their capacities can be accurately adjusted.
However, according to this structure, in order to connect a selection bit line and a non-selection line of the first and second column trees to one of the main bit lines MBL0-01 and MBL0-23, each of the blocks Bi and Bj includes the same first column selection decoder 0102 separately. As a result, since the number of circuits in the first column selection decoder is increased by two times, area of a circuit layout becomes double. As a result, this increases a total chip size.